Description:

NVIDIA, a global leader in graphics processors and AI technology, is seeking passionate ASIC Verification Engineers to join their Graphics team in Bangalore. This role involves working on state-of-the-art memory subsystem components for Graphics Processors and Tegra SOCs, impacting products from consumer graphics to self-driving cars and AI fields.

As an ASIC Verification Engineer, you will plan and implement functional verification for IP/Cluster/SOC designs, create regression plans, ensure functional and code coverage, and support pre-silicon and post-silicon validation activities. You will collaborate with hardware architects, designers, performance verification, FPGA, and software teams to ensure thorough verification and testing.

What You’ll Be Doing:

• Own ASIC verification of complex IP/Cluster RTL designs.
• Collaborate with hardware architects and designers to guide implementation decisions.
• Work with performance verification teams on dynamic simulations and formal verification techniques.
• Ensure functional and code coverage for RTL designs.
• Support FPGA and software teams for software testing.
• Participate in post-silicon verification and debugging.

Key Technical Skills:

ASIC Verification, RTL, SystemVerilog, UVM methodology, VCS (or equivalent simulators), Debug tools (Debussy, GDB), Pre-silicon validation (XPROP simulations, GLS), Functional and code coverage, Formal verification, FPGA and software integration, Post-silicon debugging

Requirements:

• Bachelor’s or Master’s degree (or equivalent experience).
• 2+ years of ASIC design and verification experience, with at least one or two projects completed.
• Experience with design and verification tools like VCS, debug tools such as Debussy or GDB.
• Strong knowledge of SystemVerilog and UVM methodology is highly desired.
• Good debugging and problem-solving skills.
• Scripting skills in Python, Perl, or shell scripting.
• Ability to work collaboratively in a team environment.

Nice to Have:

• Knowledge of Memory controllers or experience verifying IP/clusters related to memory access.